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19-1853; Rev 2; 12/02
+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs
General Description
The MAX3950 deserializer is ideal for converting 10Gbps serial data to 16-bit-wide, 622Mbps parallel data in SDH/SONET and DWDM applications. Operating from a single +3.3V supply, this device accepts CML serial clock and data inputs and delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry. The MAX3950 is available in the extended temperature range (-40C to +85C) in a 68-pin QFN package. The typical power dissipation is 900mW.
Features
o Supports Serial Data Rates Up to 10.7Gbps o 10Gbps/10.7Gbps Serial to 622Mbps/667Mbps Parallel Conversion o Single +3.3V Supply o 900mW Operating Power o CML Serial Clock and Data Inputs o LVDS Parallel Clock and Data Outputs o -40C to +85C Operating Temperature
MAX3950
Applications
SONET/OC-192 SDH/STM-64 Transmission Systems Add/Drop Multiplexers Broadband Digital Cross-Connects
PART MAX3950EGK
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 68 QFN
Pin Configuration appears at the end of data sheet.
Typical Application Circuit
VCC VCC VCC VCC 10Gbps 10Gbps OUT+ IN+ MAX3920* TIA INOUTINOUTSDISCLKO+ SCLKOSCLK+ PCLK+ SCLK100** PCLK*FUTURE PRODUCTS. **REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Zo = 50. MAX3925* AGC AMP MAX3940* CDR IN+ OUT+ 10Gbps SDI+ SDOSDOVERHEAD PROCESSING PD0+ MAX3950 DESERIALIZER PD0100** 10Gbps SDO+ SD+ PD15PD15+ 100** 622Mbps
________________________________________________________________ Maxim Integrated Products
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+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs MAX3950
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC)...............................-0.5V to +5.0V CML Input Voltage Level .................(VCC - 0.8V) to (VCC + 0.5V) LVDS Output Voltage Level........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 68-Lead QFN (derate 43.5mW/C above +85C) ......2800mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.)
PARAMETER Supply Current CML INPUTS (SD, SCLK) Differential Input Voltage Swing Single-Ended Input Voltage Range Input Termination to VCC Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output for Complementary States Offset Output Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current Short together Short to ground |VOS| 80 VID VIS RIN VOH VOL 1.025 Figure 2 150 250 25 1.15 1.25 25 120 12 24 Figure 1 400 VCC 0.6 42.5 50 1200 VCC + 0.3 57.5 1.375 mVP-P V V V mV mV V mV mA SYMBOL ICC CONDITIONS MIN TYP 270 MAX 350 UNITS mA
LVDS OUTPUT SPECIFICATION (PD[15.0] , PCLK)
|VOD|
|VOD|
2
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+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1)
PARAMETER Serial Input Data Rate Serial Data Setup Time Serial Data Hold Time Parallel Output Data Rate Parallel Output Clock Frequency Parallel Clock-to-Q Delay LVDS Output Rise/Fall Time LVDS Differential Skew LVDS Channel-to-Channel Skew Input Return Loss tSKEW1 tSKEW2 tCLK-Q (Note 2) 20% to 80% Any differential pair PD[15..0] 100kHz f 5GHz 5GHz f 10GHz 10GHz f 15GHz 200 17 14 11 dB -200 tSU tH 25 25 622 622 +200 300 65 SYMBOL CONDITIONS MIN TYP 10 MAX UNITS Gbps ps ps Mbps MHz ps ps ps ps
MAX3950
|S11|
Note 1: AC specifications are guaranteed by design and characterization. Note 2: Relative to the falling edge of PCLK+. See Figure 3.
VCC + 0.3V 600mV
VCC
200mV
VCC - 0.3V (a) AC-COUPLED CML INPUT VCC 200mV
600mV
VCC - 0.6V (b) DC-COUPLED CML INPUT
Figure 1. Input Amplitude
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+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs MAX3950
PD+ RL = 100 PDV VOD
VPDSINGLE-ENDED OUTPUT VPD+ IVODI
VOH VOS VOL
VPD+ - VPDVODP-P = 2IVODI
DIFFERENTIAL OUTPUT
0
Figure 2. Driver Output Levels
tCLK SCLK+
t SU
tH
SD
PCLK+ tCLK-Q PD
Figure 3. Timing Parameters
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+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
LVDS OUTPUT AMPLITUDE vs. TEMPERATURE
MAX3950 toc01
MAX3950
OUTPUT RISE/FALL TIME vs. TEMPERATURE
NOTE: MEASURED 20 TO 80%.
MAX3950 toc02
OUTPUT EYE DIAGRAM INPUT: 9.953Gbps, 213 - 1 +100 ZEROS PRBS
MAX3950 toc03
250 SINGLE-ENDED LVDS OUTPUT (mVP-P) 240 230 220 210 200 190 180 170 160 150 -40 -20 0 20 40 60 80 AMBIENT TEMPERATURE (C)
300 250 RISE/FALL TIME (ps) 200
PCLK+
DATA 150 CLOCK 100
PCLK-
PD 50 0 -40 -20 0 20 40 60 80 200ps/div AMBIENT TEMPERATURE (C)
OUTPUT EYE DIAGRAM INPUT: 10.7Gbps, 213 - 1 +100 ZEROS PRBS
MAX3950 toc04
INPUT RETURN LOSS
NOTE: DATA IS FROM SIMULATION AND INCLUDES PACKAGE PARASITICS.
MAX3950 toc05
0 -5 RETURN LOSS (dB) -10 -15 -20 -25 -30
PCLK+
PCLK-
PD
200ps/div
0
5
10 FREQUENCY (GHz)
15
20
Pin Description
PIN 1, 2, 5, 13, 16, 17, 18, 26, 33-36, 42, 51, 52, 53, 60, 68 6, 9, 12, 25, 31, 32, 37, 43, 50, 54, 55, 61 7 8 10 11 14 NAME FUNCTION
GND
Ground
VCC SD+ SDSCLK+ SCLKPCLK-
Positive Power Supply Positive Data Input. 9.953Gbps serial data stream, CML. Negative Data Input. 9.953Gbps serial data stream, CML. Positive Serial Clock Input. 9.953GHz, CML. Negative Serial Clock Input. 9.953GHz, CML. Negative Parallel Clock Output, 622.08MHz, LVDS.
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+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs MAX3950
Pin Description (continued)
PIN 15 19, 21, 23, 27, 29, 38, 40, 44, 46, 48, 56, 58, 62, 64, 66, 3 20, 22, 24, 28, 30, 39, 41, 45, 47, 49, 57, 59, 63, 65, 67, 4 EP CP NAME PCLK+ PD0- to PD15PD0+ to PD15+ Exposed Pad Corner Pins FUNCTION Positive Parallel Clock Output, 622.08MHz, LVDS. Negative Parallel Data Output, 622.08Mbps, LVDS.
Positive Parallel Data Output, 622.08Mbps, LVDS.
Ground. This must be soldered to the circuit board ground for proper thermal and electrical operation. See Layout Considerations. N.C. Not Connected. Ensure that the solder mask is located below them so that unintentional connections do not occur.
MAX3950 DATA D FLIP-FLOP DELAY DIVIDE BY 4
4-BIT SHIFT REGISTER 4-BIT SHIFT REGISTER 4-BIT SHIFT REGISTER 4-BIT SHIFT REGISTER DIVIDE BY 4
CML INPUT
CLK
CML INPUT
OUTPUT REGISTER
DATA CLK
Figure 4. Functional Block Diagram
Detailed Description
The MAX3950 deserializer implements a shift-registerbased demultiplexer to convert 9.953Gbps serial data to 16-bit-wide, 622.08Mbps parallel data (Figure 4). The allocation of the serial input bits to the parallel LVDS outputs is displayed in Figure 5.
Applications Information
Low-Voltage Differential-Signal Outputs
The MAX3950 features LVDS outputs for interfacing with high-speed digital circuitry. This LVDS implementation is based on the IEEE 1596.3 LVDS reduced-range link specification and is compatible with OIF 1999.102.
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Note that the PCLK polarity on the MAX3950 is inverted relative to OIF 1999.102, so that PCLK+ is equivalent to RXCLK_N and PCLK- is equivalent to RXCLK_P. The MAX3950 uses 300mVP-P to 500mVP-P differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. The parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100 differential DC termination between the inverting and noninverting outputs for proper operation. Do not terminate these outputs to ground. For more information on interfacing with the LVDS outputs, refer to Maxim Application Note HFAN1.0: Interfacing Between CML, PECL, and LVDS.
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+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs MAX3950
D15 D14 D13
SD
PCLK+
(LSB) PD0
D0
D16
D32
D48
D64
PD1 * * * (MSB) PD15 TRANSMITTED FIRST
D1
D17
D33
D49
D65
D15
D31
D47
D63
D79
Figure 5. Timing Diagram
VCC
250fF 1.1nH SD+ K = 0.4 SD1.1nH 250fF
50
50
HIGH Z 70fF 70fF HIGH Z
NOTE: PARASITIC VALUES SHOWN ARE TYPICAL VALUES.
Figure 6. CML Input Model
Current Mode Logic (CML) Inputs
The differential serial inputs to the MAX3950 are CML and have an input impedance of 50 on each of the complementary inputs. For more information on interfacing with the CML inputs, refer to Maxim Application Note HFAN-1.0: Interfacing Between CML, PECL, and LVDS.
Layout Considerations
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3950's high-speed inputs and outputs. Place power-supply decoupling as close to VCC as possible. To reduce feedthrough, isolate the input signals from the output signals.
Interface Models
Figures 6 and 7 show the typical input/output models for the MAX3950 deserializer.
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+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs MAX3950
Chip Information
vcc
TRANSISTOR COUNT: 4800
vcc PD_+ vcc PD_-
MAX3950
Figure 7. LVDS Output Model
Pin Configuration
TOP VIEW
PD14+ PD13+ PD12+ PD11+ PD10+
PD14-
PD13-
PD12-
PD11-
PD10-
GND
GND
GND
GND GND
VCC
VCC
VCC
68 1 2 3 4 5 6 7 8 9
67 66 65 64 63 62
61 60 59 58 57 56 55 54 53 52
GND GND PD15PD15+ GND VCC SD+ SDVCC
51 GND 50 VCC 49 PD9+ 48 PD947 PD8+ 46 PD845 PD7+ 44 PD743 VCC 42 GND 41 PD6+ 40 PD639 PD5+ 38 PD537 VCC 36 GND 35 GND 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
MAX3950
SCLK+ 10 SCLK- 11 VCC 12 GND 13 PCLK- 14 PCLK+ 15 GND 16 GND 17
N. C.
PD0+
PD0-
PD1-
PD1+
PD2-
PD2+
GND
PD3-
PD3+
PD4-
PD4+
GND
*EXPOSED PAD IS CONNECTED TO GND.
QFN*
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GND
VCC
VCC
VCC
N. C. N.
C.
N. C.
+3.3V, 10.7Gbps 1:16 Deserializer with LVDS Outputs MAX3950
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
9 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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